學(xué)員學(xué)習(xí)本課程應(yīng)具備下列基礎(chǔ)知識(shí)：
        ◆ 電路系統(tǒng)的基本概念。

        1、培訓(xùn)過(guò)程中，如有部分內(nèi)容理解不透或消化不好，可免費(fèi)在以后培訓(xùn)班中重聽(tīng)；
        2、培訓(xùn)結(jié)束后,授課老師留給學(xué)員聯(lián)系方式,保障培訓(xùn)效果,免費(fèi)提供課后技術(shù)支持。
        3、培訓(xùn)合格學(xué)員可享受免費(fèi)推薦就業(yè)機(jī)會(huì)。

• What is functional verification and what is being verified　
  Formal Verification,Equivalence Checking,Model checking,
  Functional Verification,Test Bench Generation
• Functional Verification Approaches
  Black-Box,White-Box,Grey-Box
• The Verification Process
• Specification and Test Plan ((Specification->Features->Test cases)
  Direct 、Direct-Random and Random Test Case
• Advanced Verification Methodology
• System//Chip/Module Level Verification
• Behavioral Hardware Description Languages
• Stimulus and Response
  Generating complex waveforms,Self-Checking test benches,Complex
  Response,Predicting the output
• How to build reusable test bench
• Test Bench Acceleration
• Coverage Analysis in the Design Flow
• Feature Coverage and Code Coverage (Line Condition Toggle FSM)
  Coding Guidelines
  Structure,Naming Convention,Comments,Syntax,Debugging
• Simulation Management
  Modeling reset,Writing Good Behavioral Model,Regression Management

• Assertions Methodology
• Formal Verification ((Design Rule Check)
• Vector--based Verification
• Memory Verification
• Project Management and Verification Experience
  Introduce the useful verification experience that have been
  successfully used to produce one-passed ASICs,SoC,board,and
  entire systems.
• Verisity 's Specman e language
• Verisity 's e VC(e Verification Component)
• Verisity 's e RM(e Reuse Methodlogy)