1、培訓過程中，如有部分內(nèi)容理解不透或消化不好，可免費在以后培訓班中重聽；
        2、培訓結(jié)束后,授課老師留給學員聯(lián)系方式,保障培訓效果,免費提供課后技術支持。
        3、培訓合格學員可享受免費推薦就業(yè)機會。

培訓安排：

第一階段：

概述

SOCEncounter的基本界面操作

布圖（Floorplan）

電源網(wǎng)絡設計（power?plan）

布局（Placement）

掃描鏈重排與優(yōu)化（Scan?Chain?Re-ordering）

早期布線特性分析（TrialRoute）

1) Advance and High performance design challenged– Encounter solution-RCP

Traditional synthesis tools use vendor-supplied wire-load models based on fanouts, which do not provide accurate wire delay information especially for designs where a significant portion of the delays are contributed by the wires. The RCP flow uses a complete placement and considers congestion and legal placement as a cost function during the RTL-to-gates phase, to create a better netlist. This flow ensures both the best accuracy and the most predictable closure with back-end tools.

-CCOPT

Clock Concurrent Optimization technology, also known as CCopt, which delivers superior capabilities for designers faced with increasing performance, power and area challenges. Specifically, ccopt technology has delivered significant quality of silicon (QoS) on high-speed processor designs in the areas of:

n ?Power (clock tree power reduction up to 30 percent and total power improvements of up to 10 percent),

?

n ?Performance (improvements of up to 100 MHz for a GHz design), and

n ?Area (clock tree area reduction up to 30 percent)

-GigaOpt

The new GigaOpt technology inside EDI System produces high-quality results faster than traditional optimization engines by harnessing the power of multiple CPUs. GigaOpt does multi-threading combined base and SI delay timing optimization.

2) ?Mixed Signal Physical Implementation flow

- Introduction

- Integration Constraints

- Netlist Driven Mixed Signal Flow

3) ?RDL co-design flow

- Flipchip introduce

- Encounter Flipchip flow

- RDL co-design

In this course, you willRun timing optimization?
Run silicon virtual prototyping?
Run placement with the Amoeba placer?
Estimate parasitics and generate delay information?
Analyze congestion after running Trial Route?
Create clock trees?
Create physical partitions (hierarchy) and timing budgets?
Run signal integrity analysis?
Optimize timing?
Run NanoRoute? Ultra detail routing?
Apply postroute timing and signal integrity optimization
In this course, you will get a high-level technical overview of the SoC Encounter flow. However, to gain in-depth knowledge about each tool, refer to the Related Courses list and take the corresponding course(s).

　　 Synthesis flow?
　　 Application of design constraints?
　　 Optimization strategies?
?
　　 Synthesis of datapath structures?
　　 Synthesis for low power?
　　 Interface to place and route?
　　 Design for testability (optional)?

第二階段：

q Selecting and Highlighting Objects in the Design

q Floorplanning the Design

q Planning Power?

q Running Detail Placement

q Scan Optimization and Reordering

q Analyzing Route Feasibility with?Trial Route

q Extracting Parasitics and Analyzing Timing

q Multi-Mode Multi-Corner Analysis

q Optimizing and Closing Timing

q Implementing the Clock Tree

q Routing Power with?Special Route

q Analyzing Power Routing Optimization

q Routing for Signal Integrity, Timing, and Design for Yield

q Evaluating Routing Problems

q Wire Editing

q Signal Integrity

寄生參數(shù)提取和靜態(tài)時序分析（Extraction?and?STA）

多模多角分析（MMMC）

時序優(yōu)化（Timing?Optimization）

時鐘樹生成（CTS）

電源網(wǎng)絡布線（Special?Route）

功耗分析（Power?Analysis）

第三階段：Laker Schematic Driven Layout Training