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上課地點：【上�！浚和瑵髮W(滬西)/新城金郡商務樓(11號線白銀路站) 【深圳分部】：電影大廈(地鐵一號線大劇院站)/深圳大學成教院【北京分部】：北京中山學院/福鑫大樓【南京分部】：金港大廈(和燕路) 【武漢分部】：佳源大廈（高新二路）【成都分部】：領館區1號（中和大道）【沈陽分部】：沈陽理工大學/六宅臻品【鄭州分部】：鄭州大學/錦華大廈【石家莊分部】：河北科技大學/瑞景大廈【廣州分部】：廣糧大廈【西安分部】：協同大廈
最近開課時間(周末班/連續班/晚班）：Synopsys Prime Time 1 培訓班：2020年3月16日

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　　　　　　　　Synopsys Prime Time 1 培訓班

本課程可幫助IC工程師進一步全面系統地理解IC設計概念與方法。培訓將采用Synopsys公司相關領域的培訓教材，培訓方式以講課和實驗穿插進行。

Overview
This workshop shows you how to maximize your productivity when using PrimeTime. You will validate and enhance run scripts, quickly identify and debug your design violations by generating and interpreting timing reports, remove pessimism with path-based analysis, and generate ECO fixing guidance to downstream tools.

Topics include:

Preparing for STA on your design, including investigating and analyzing the clocks that dictate STA results
Validating inherited PrimeTime run scripts
Leveraging the latest PrimeTime best practices to create new run scripts
Identifying opportunities to improve run time
Performing static timing analysis
Providing ECO fixing guidance to downstream tools

Objectives

At the end of this workshop the student should be able to:

Interpret the essential details in a timing report for setup and hold, recovery and removal, and clock-gating setup and hold
Generate timing reports for specific paths and with specific details
Generate summary reports of the design violations organized by clock, slack, or by timing check
Validate, confirm, debug, enhance, and execute a PrimeTime run script
Create a PrimeTime run script based on seed scripts from the RMgen utility
Identify opportunities to improve run time
Create a saved session and subsequently restore the saved session
Identify the clocks, where they are defined, and which ones interact on an unfamiliar design
Reduce pessimism using path-based analysis
Use both a broad automatic flow for fixing setup and hold violations and a manual flow for tackling individual problem paths.

Audience Profile
Design or verification engineers who perform STA using PrimeTime.

Prerequisites
To benefit the most from the material presented in this workshop, students should have:

A basic understanding of digital IC design
Familiarity with UNIX workstations running X-windows
Familiarity with vi, emacs, or other UNIX text editors

Course Outline

階段一

Does your design meet timing?
Objects, Attributes, Collections
Constraints in a timing report
Timing arcs in a timing report
Control which paths are reported

階段二

Summary Reports
Create a setup file and run script
Getting to know your clocks
Analysis types and back annotation

階段三

Additional checks and constraints
Path-Based Analysis and ECO Flow
Emerging Technologies and Conclusion