1. Synopsys SystemVerilog驗證培訓(xùn)
   課程描述：
   第一階段 SystemVerilog Assertions培訓(xùn)
2. COURSE OUTLINE
   * Introduction to assertions
   * SVA checker library
   * Use Model and debug flow using DVE
   * Basic SVA constructs
   * Temporal behavior, Data Consistency
   * Coverage, Coding Guidelines
3. 第二階段 SystemVerilog Testbench
4. Overview
5. In this intensive, three-day course, you will learn the key features and benefits of the SystemVerilog testbench language and its use in VCS.
   This course is a hands-on workshop that reinforces the verification concepts taught in lecture through a series of labs. At the end of this class, students should have the skills required to write an object-oriented SystemVerilog testbench to verify a device under test with coverage-driven constrained-random stimulus using VCS.
   Students will first learn how to develop an interface between the SystemVerilog test program and the Device Under Test (DUT). Next the workshop will explain how the intuitive object-oriented technology in SystemVerilog testbench can simplify verification problems. Randomization of data is covered to show how different scenarios for testing may be created. This course concludes with an in-depth discussion of functional coverage including a uniform, measurable definition of functionality and the SystemVerilog constructs that allow you to assess the percentage of functionality covered, both dynamically and through the use of generated reports.
   To reinforce the lecture and accelerate mastery of the material, each student will complete a challenging test suite for real-world, system-based design.
   Objectives
   At the end of this workshop the student should be able to:
   Build a SystemVerilog verification environment
   Define testbench components using object-oriented programing.
   Develop a stimulus generator to create constrained random test stimulus
   Develop device driver routines to drive DUT input with stimulus from generator
   Develop device monitor routines to sample DUT output
   Develop self-check routines to verify correctness of DUT output
   Abstract DUT stimulus as data objects
   Execute device drivers, monitors and self-checking routines concurrently
   Communicate among concurrent routines using events, semaphores and mailboxes
   Develop functional coverage to measure completeness of test
   Use SystemVerilog Packages
   Course Outline
   Uunit 1
   The Device Under Test
   SystemVerilog Verification Environment
   SystemVerilog Testbench Language Basics
   Driving and Sampling DUT Signals
   Uunit 2
   Managing Concurrency in SystemVerilog
   Object Oriented Programming: Encapsulation
   Object Oriented Programming: Randomization
   Uunit 3
   Object Oriented Programming: Inheritance
   Inter-Thread Communications
   Functional Coverage
   SystemVerilog UVM preview
   
6. 第三階段 Synopsys SystemVerilog VMM培訓(xùn)
7. SystemVerilog Verification Using VMM Methodology
   OVERVIEW
   In this hands-on workshop, you will learn how to develop a VMM SystemVerilog test environment structure which can implement a number of different test cases with minimal modification. Within this VMM environment structure, you will develop stimulus factories, check and coverage callbacks, message loggers, transactor managers, and data flow managers. Once the VMM environment has been created, you will learn how to easily add extensions for more test cases.
   After completing the course, you should have developed the skills to write a coverage-driven random stimulus based VMM testbench that is robust, re-useable and scaleable.
   OBJECTIVES
   At the end of the course you should be able to:
   Develop an VMM environment class in SystemVerilog
   Implement and manage message loggers for printing to terminal or file
   Build a random stimulus generation factory
   Build and manage stimulus transaction channels
   Build and manage stimulus transactors
   Implement checkers using VMM callback methods
   Implement functional coverage using VMM callback methods
   COURSE OUTLINE
   Unit 1
   SystemVerilog class inheritance review
   VMM Environment
   Message Service
   Data model
   Unit 2
   Stimulus Generator/Factory
   Check & Coverage
   Transactor Implementation
   Data Flow Control
   Scenario Generator
   Recommendations
8. 第四階段 SystemVerilog Verification using UVM
   Overview
   In this hands-on workshop, you will learn how to develop a UVM 1.1 SystemVerilog testbench environment which enables efficient testcase development. Within this UVM 1.1 environment, you will develop stimulus sequencer, driver, monitor, scoreboard and functional coverage. Once the UVM 1.1 environment has been created, you will learn how to easily manage and modify the environment for individual testcases.
   Objectives
   At the end of this workshop the student should be able to:
   Develop UVM 1.1 tests
   Implement and manage report messages for printing to terminal or file
   Create random stimulus and sequences
   Build and manage stimulus sequencers, drivers and monitors
   Create configurable agents containing sequencer, driver and monitor for re-use
   Create and manage configurable environments including agents, scoreboards, TLM ports and functional coverage objects
   Implement a collection of testcases each targeting a corner case of interest
   Create an abstraction of DUT registers and manage these registers during test, including functional coverage and self-test
   Audience Profile
   Design or Verification engineers who develop SystemVerilog testbenches using UVM 1.1 base classes.
   Prerequisites
   To benefit the most from the material presented in this workshop, students should have completed the SystemVerilog Testbench workshop.
   Course Outline
   Unit 1
   SystemVerilog OOP Inheritance Review
   Polymophism
   Singleton Class
   Singleton Object
   Proxy Class
   Factory Class
   UVM Overview
   Key Concepts in UVM: Agent, Environment and Tests
   Implement UVM Testbenches for Re-Use across Projects
   Code, Compile and Run UVM Tests
   Inner Workings of UVM Simulation including Phasing
   Implement and Manage User Report Messages
   Modeling Stimulus (Transactions)
   Transaction Property Implementation Guidelines
   Transaction Constraint Guidelines
   Transaction Method Automation Macros
   User Transactiom Method Customization
   Implement Tests to Control Transaction Constraints
   Creating Stimulus Sequences
   Sequence Execution Protocol
   Using UVM Macros to create and manage Stimulus
   Implementing User Sequences
   Implicitly Execute Sequences Through Configuration in Environment
   Explicitly Execute Sequences in Test
   Control Sequences through Configuration
   Unit 2
   Component Configuration and Factory
   Establish and Query Component Parent-Child Relationships
   Set Up Component Virtual SystemVerilog Interfaces with uvm_config_db
   Constructing Components and Transactions with UVM Factory
   Implement Tests to Configure Components
   Implement Tests to Override Components with Modified Behavior
   TLM Communications
   TLM Push, Pull and Fifo Modes
   TLM Analysis Ports
   TLM Pass-Through Ports
   TLM 2.0 Blocking and Non-Blocking Transport Sockets
   DVE Waveform Debugging with Recorded UVM Transactions
   Scoreboard & Coverage
   Implement scoreboard with UVM In-Order Class Comparator
   Implement scoreboard UVM Algorithmic Comparator
   Implement Out-Of-Order Scoreboard
   Implement Configuration/Stimulus/Correctness Coverage
   UVM Callback
   Create User Callback Hooks in Component Methods
   Implement Error Injection with User Defined Callbacks
   Implement Component Functional Coverage with User Defined Callbacks
   Review Default Callbacks in UVM Base Class
   Unit 3
   Virtual Sequence/Sequencer
   Disable Selected Sequencer in Agents through the Sequencer抯 揹efault? Configuration Field
   Implement Virtual Sequence and Sequencer to Manager Sequence Execution within Different Agents
   Implement uvm_event for Synchronization of Execution among Sequences in the Virtual Sequence
   Implement Grab and Ungrab in Sequences for exclusive access to Sequencer
   More on Phasing
   Managing Objections within Component Phases
   Implement Component Phase Drain Time
   Implement Component Phase Domain Synchronization
   Implement User Defined Domain and Phases
   Implement UVM Phase Jumping
   Register Layer Abstraction (RAL)
   DUT Register Configuration Testbench Architecture
   Develop DUT Register Abstration (.ralf) File
   Use ralgen Utility to Create UVM Register Model Class Files
   Create UVM Register Adapter Class
   Develop and Execute Sequences Using UVM Register Models
   Use UVM Built-In Register Tests to Verify DUT Register Operation
   Enable RAL Functional Coverage
   Summary
   Review UVM Methodology
   Review Run-Time Command Line Debug Switche
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